In many of today's micro-electronics, smaller more compact sizing yields greater speed and processing power. Improved materials and precision in manufacturing permit greater resolutions in semiconductor manufacturing.
Generally speaking, semiconductors are manufactured through a layering process that provides two or more patterned conductive layers separated by intervening insulation layers. Considering the layers to be horizontally stacked, vertical points of contact between two or more conductive layers through the insulation layers are known as via structures, or more generally, via contacts. It is these via contacts that provide the wiring pattern for the integrated circuit.
Today's computer systems employ a variety of different types of semiconductors such as processors and memory. Increasing speed and sophistication of the systems is due in large part to reducing the size of the semiconductor components. For example, whereas 32 megabytes of memory was once considered large, contemporary computer systems may provide several gigabytes in substantially the same physical space.
With respect to memory structures, and specifically magnetic tunnel junction structures, the principle underlying the storage of data in the magnetic media is the ability to change, and or reverse, the relative orientation of magnetization of a storage data bit (i.e. the logic state of a “0” or a “1”). A prior art magnetic memory cell may be a tunneling magnetoresistance memory cell (TMR), a giant magnetoresistance memory cell (GMR), or a colossal magnetoresistance memory cell (CMR), each of which generally includes a data layer (also called a storage layer or bit layer), a reference layer, and an intermediate layer between the data layer and the reference layer.
It is this collection of layers defining the magnetic tunnel memory cell that are placed between two or more parallel conductive layers. The via contacts at the top of each magnetic tunnel memory permit the top conductor to provide electrical current to the memory cell.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer and the reference layer. For example, assuming proper contact with the via contacts at the top of the cell, when an electrical potential bias is applied across the data layer and the reference layer in a TMR cell, electrons migrate between the data layer and the reference layer through the intermediate layer. The intermediate layer is typically a thin dielectric layer commonly referred to as a tunnel barrier layer. The phenomena that cause the migration of electrons through the barrier layer may be-referred to as quantum mechanical tunneling or spin tunneling. The logic state may be determined by measuring the resistance of the memory cell.
Prior art methods to accomplish conductive vertical interconnections between layers of materials have generally followed one of two paths. In one, a physical hole is etched, as in drilled, through a non-conductive layer and subsequently filled with a conductive material. Such etching or drilling requires fine precision and control, for too much etching or drilling may damage, deplete or entirely remove the underlying layer to which the via contact is intended to contact. An alternative and potentially less risky method involves the use of undercutting masking structures, which upon removal may provide a via contact.
The prior art methods of semiconductor device manufacturing are typically based on photolithography. Generally speaking, a conductive layer of material is set down on a substrate. A photo-resist layer, also commonly know simply as a photoresist, or even resist, is then applied typically with a spin coating machine. A mask is then placed over the photoresist and light, typically UV light, is applied. During the process of exposure, the photoresist undergoes a chemical reaction. Generally the photoresist will react in one of two ways. With a positive photoresist UV light changes the chemical structure of the photoresist so that it is soluble in a developer. What “shows” therefore goes, and the mask provides an exact copy of the pattern which is to remain. A negative photoresist behaves in the opposite manner—UV exposure causes it to polymerize and therefore photoresist dissolving by the developer. As such the mask is a photographic negative of the pattern to be left.
FIGS. 1A through 2C illustrate the typical process involving the use of bi-layer resists to provide a photoresist undercut and subsequent via contacts. Shown in FIG. 1A is a portion of a magnetic memory structure 100 undergoing fabrication. The magnetic memory structure 100 is comprised of a substrate 102, row conductors 104, dielectric insulation 106, and the raw components of what will ultimately comprise the magnetic tunnel junction, for simplicity here referred to as the junction stack 108.
A first photoresist layer 110 is applied to the top of the junction stack 108 and a mask 112 is provided and light 116, typically UV, is provided. As the photoresist is a positive resist, the exposed area is made susceptible to decomposition upon contact with developer. In FIG. 1B, a second photoresist layer 120 is then applied atop the first photoresist layer 110 before the process of developing. A second mask 122 and additional light 116 are also provided. As can be seen, the masked areas 124 of the second mask 122 are larger than the mask areas 114 of the first mask 112.
By masking a larger area of the second photoresist 120 the resulting bi-layer of photoresist will provide an undercut stacked structure, akin to a photoresist mushroom 200, upon developing, as is shown in FIG. 2A. Each photoresist mushroom has an undercut portion 202 as a base and a cap 204. Etching is then performed upon the junction stack to create individual junction stacks 206 for each memory cell 208. A dielectric coating 220 is then applied over the exposed fabrication surface. As can be seen the dielectric coating 220 tends to coat exposed horizontal and exposed surfaces. The undercut portions 202 of the photoresist mushrooms 200 are generally not coated. A photoresist dissolving agent is then applied and the exposed undercut portions 202 of the photoresist mushrooms 200 are dissolved and the caps 204 washed away, leaving exposed via contacts 230 (see FIG. 2C).
To assist and further insure the undercutting process during development, resists with different development speeds may be used as well. More specifically the first photoresist 110 may develop faster then the second photoresist 120, thus the first photoresist 110 dissolves away more quickly then the second photoresist 120. In yet another traditional undercutting bi-layer photoresist process, photoresists requiring different developing agents may be used. In such an instance the two photoresist layers 110 and 120 are applied and one mask 122 may be used. The photoresists 120 and 110 are then developed with their respective developers. The undercut of photoresist 110 is achieved by over or under developing photoresist layer 110, depending on the type of photoresist utilized.
The process of creating the undercut photoresist mushrooms 200 whether by multiple masking, by using resists of different developing speeds, or a combination of both masking and different developing speeds is complex, time consuming and difficult. As the size of the memory cells 208 may be on the scale of nanometers, there is little margin for error. If the undercut portion 202 fails to form properly the memory cell 208 may be nonfunctional. In addition, if the dielectric coating 220 is applied too thick, it may bridge over the undercut portions 202 and shield them from the dissolving agent, thus preventing the exposure of the via contact 230. Also, as the undercut portion 202 is smaller than the shielding cap 204, the via contact 230 ultimately provided is by some degree smaller than the top of the memory cell 208 and does not provide the maximum contact area possible. Therefore, the maximum density of memory cells provided by an undercut process is limited by the size of the via contact 230 and the complexities of the bi-layer undercut process, rather than the size of the individual junction stack 206 or the limitations of the photolithography process. Further, during the process of washing away the solid coated caps 204, it is possible that as they are solid structures they may collide with memory cells 208 damaging them immediately, or making them susceptible to premature failure.
Hence, there is a need for a method of providing via contacts during semiconductor fabrication, and in particular magnetic memory cells, which overcomes one or more of the drawbacks identified above. The present invention satisfies one or more of these needs.